Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed.
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Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed.
Imprint | Springer-Verlag New York |
Country of origin | United States |
Series | Analog Circuits and Signal Processing |
Release date | March 2009 |
Availability | Expected to ship within 10 - 15 working days |
First published | 2009 |
Authors | Pedro M. Figueiredo, Joao C. Vital |
Dimensions | 235 x 155 x 23mm (L x W x T) |
Format | Hardcover |
Pages | 382 |
Edition | 2009 ed. |
ISBN-13 | 978-1-4020-9715-7 |
Barcode | 9781402097157 |
Categories | |
LSN | 1-4020-9715-8 |