This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.
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This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.
Imprint | Springer-Verlag New York |
Country of origin | United States |
Series | Integrated Circuits and Systems |
Release date | November 2010 |
Availability | Expected to ship within 10 - 15 working days |
First published | 2007 |
Authors | Prashant Saxena, Rupesh S Shelar, Sachin Sapatnekar |
Dimensions | 235 x 155 x 14mm (L x W x T) |
Format | Paperback |
Pages | 250 |
Edition | Softcover reprint of hardcover 1st ed. 2007 |
ISBN-13 | 978-1-4419-4013-1 |
Barcode | 9781441940131 |
Categories | |
LSN | 1-4419-4013-8 |